As microelectronic device dimensions continue to shrink, patterning problems increasingly hinder integrated circuit and semiconductor device fabrication. Semiconductor device fabrication often requires extremely planar surfaces and thin films of precise thicknesses. The surfaces requiring planarization and thickness control in semiconductor devices include areas or layers of dielectric material (such as SiO2) on the surface of semiconducting materials and other device pattern layers. The insulating dielectric layers and other device layers need to be extremely planar because irregularities and rough topography lead to fabrication problems, including Depth of Focus budget (hereafter DOF) problems. Since an irregularity in the surface can cause part of the surface to be out of focus at a particular distance between the optical system and the wafer, errors in pattern formations can occur. Also, the thickness of layers needs to be precisely controlled because variations in thickness may affect the electrical properties of the layers and adjacent device patterns, particularly in the interconnections between the different layers of microelectronic devices.
The precise control of layer thickness is also crucial in semiconductor device fabrication. In VLSI technology, certain layers of multi-layer devices are generally electrically interconnected. These layers are also typically insulated from various levels by thin layers of insulating material such as SiO.sub.2. In order to interconnect the device layers, contact holes are often formed in the insulating layers to provide electrical access therebetween. If the insulating layer is too thick, the layers may not connect, if the layer is too thin, the hole formation process may damage the underlying device layer.
Due to the various inadequacies of other planarization methods (such as spin-on-glass and etchback), Chemical/Mechanical Polishing (hereafter CMP) planarization machines and other lapping machines have been developed and employed to provide planar surfaces for semiconductor device fabrication. Generally, CMP is a technique of planarizing wafers through the use of a polishing pad attached to a rotating table. The wafer is held by a chuck above a polishing pad which rotates on a spindle. The wafer is pressed downward against the polishing pad. The nap of the rotating pad removes bits of the film layer, thereby planarizing the surface. A solution of pH controlled fluid and colloidal silica particles called slurry flows between the pad and the wafer to remove material from the polishing area and to enhance the planarization of the wafer surface.
A typical method of determining the endpoint of CMP and lapping machines is to measure the amount of time needed to planarize standard wafer(s), and then to process the remaining wafers for a similar amount of time. In practice, this process is very inefficient because it is very difficult to determine the precise rate of film removal, as polishing conditions and the polishing pad change from wafer to wafer over time. As a result, it is often necessary to inspect the wafers individually after planarization, which is time-consuming and expensive. Thus, the CMP process could be significantly improved by introducing an in situ, real-time measurement and control system.
The ability to monitor and control the CMP process has been directly and indirectly addressed by several techniques. One method is based on measuring capacitance (U.S. Pat. No. 5,081,421). The theory behind this method is that the electrical capacitance of the wafer changes as the wafer surface is planarized. The two primary drawbacks of the method are its limited accuracy and its pattern dependency. Its accuracy can be compromised by the patterns of underlying layers which may also affect the capacitance of the entire system.
One direct method has been proposed which uses laser light to make interferometric readings on the polished side (front side) of a section of the wafer which overhangs the polishing pad (U.S. Pat. No. 5,081,796). The disadvantages of this system are that it requires substantial modification of the conventional CMP process since part of the wafer must overhang the edge of the polishing pad, leading to polishing uniformity problems, and also, the monitored spot on the rotating wafer must be coordinated with the apparatus underneath the wafer overhang.
An indirect method of monitoring CMP has been developed which senses the change in friction between the wafer and the polishing surface (U.S. Pat. No. 5,036,015). The change in friction may be produced when, for instance, an oxide coating of the wafer is removed and a harder material is contacted by the polishing pad. The accuracy of the method suffers from variations in changing pad conditions. In addition, use of the method may be limited by the need to sense the friction generated by different materials.
Another indirect method of monitoring CMP has been developed utilizing the conductivity of the slurry during polishing (U.S. Pat. No. 4,793,895). When metal layers are exposed during the CMP process, the electrical resistivity of the slurry and wafer changes due to the exposed metal on the wafer surface. The obvious drawback of this method is that it requires having exposed metal surfaces for monitoring. This is not possible for most types of polishing situations.
Another indirect method of monitoring CMP has been developed utilizing the waste slurry off the pad during planarization (U.S. Pat. No. 4,879,258). Certain materials are imbedded in the dielectric layer and monitored as they are planarized and fall off the polishing pad. The obvious drawbacks to this method include the time delay between planarization and when the slurry reaches the edge of the pad (estimated to be approximately 30 seconds) and also the low levels of sensitivity and signal noise introduced by the materials left over from the previous wafers. This method is not an active, real-time method.
These and other endpoint detection techniques do not offer effective and accurate control of the CMP process in an in situ, real-time manner. These schemes either compromise the accuracy of the endpoint detection and/or require significant alterations of the CMP process.